71T75902中文资料2.5V 1M x 18 ZBT Synchronous 2.5V I/O Flow-through SRAM数据手册Renesas规格书

描述 Description

The 71T75902 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround.

特性 Features

Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the need to control OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V (±5%) I/O Supply (VDDQ)
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Available in 100-pin TQFP and 119-pin BGA packages