6V31021数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

描述 Description

The IDT6V31021 is a 4-output low- power differential buffer. Each output has its own OE# pin. It has a maximum operating frequency of 167 MHz and supports all SERDES clock frequencies for Freescale QorIQ CPUs.

特性 Features

4 - low power differential output pairs
Individual OE# control of each output pair
Low power differential outputs
Power down mode when all OE# are high
Industrial temperature range
20-pin MLF
Output cycle-cycle jitter <15 ps additive
Output to Output skew: <50 ps
PCIe Gen3 addtive phasejitter <0.3 ps rms
10.3125G / 64 additive phase jitter <100 fs rms