670M-01LF集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Features

• Packaged in 16-pin SOIC

• Pb (lead) free package, RoHS compliant

• Clock inputs from 5 to 160 MHz (see page 2)

• Patented PLL with low phase noise

• Output clocks up to 160 MHz at 3.3 V

• 15 selectable on-chip multipliers

• Power down mode available

• Low phase noise: -124 dBc/Hz at 10 kHz

• Output enable function tri-states outputs

• Low jitter–15 ps one sigma

• Full swing CMOS outputs with 25 mA drive capability at

TTL levels

• Advanced, low power, sub-micron CMOS process

• Industrial temperature version available

• Operating voltage of 3.3 V or 5 V