66AK2G01中文资料Multicore DSP+ARM KeyStone II System-on-Chip (SoC)数据手册TI规格书

描述 Description

66AK2G0x is a family of heterogeneous multicore System-on-Chip (SoC) devicesbased on TI’s field-proven Keystone II (KS2) architecture. These devices address applications thatrequire both DSP and ARM performance, with integration of high-speed peripheral and memoryinterfaces, hardware acceleration for network and cryptography functions, and high-level operatingsystems (HLOS) support.
Similar to existing KS2-based SoC devices, the 66AK2G0x enables both the DSP and ARM cores to master all memory andperipherals in the system. This architecture facilitates maximum software flexibility where eitherDSP- or ARM-centric system designs can be achieved.
The 66AK2G0x significantly improves device reliability by extensivelyimplementing error correction code (ECC) in processor cores, shared memory, embedded memory inmodules, and external memory interfaces. Full analysis of soft error rate (SER) and power-on-hours(POH) shows that the designated 66AK2G0x parts satisfy a wide range ofindustrial and automotive requirements.
Accompanied by the new Processor SDK, the 66AK2G0x development platform enablesunprecedented ease-of-use with main line open source Linux, CCS 6.x, a wide range of OS-independentdevice drivers, as well as TI-RTOS that enables seamless task management across processor cores.The device also features advanced debug and trace technology with the latest innovations from TIand ARM, such as system trace and seamless integration of the ARM CoreSight components.
Secure boot can also be made available for anticloning and illegal software updateprotection. For more information about secure boot, contact your TI salesrepresentative.

特性 Features

·Processor Cores:
·ARM® Cortex®-A15 Microprocessor Unit (ARM A15) Subsystem at up to 600 MHz·Supports Full Implementation of ARMv7-AArchitecture Instruction Set
·Integrated SIMDv2 (NEON™ Technology) and VFPv4 (Vector FloatingPoint)
·32KB of L1 Program Memory
·32KB of L1 Data Memory
·512KB of L2 Memory
·Error Correction Code (ECC) Protectionfor L1 Data Memory ECC for L2 Memory
·Parity Protection for L1 ProgramMemory
·Global Timebase Counter (GTC)· 64-Bit Free-Running Counter That Provides Timebase for ARM A15 InternalTimers
· Compliant to ARM V7 MPCore Architecture for Generic Timers


·C66x Fixed- and Floating-Point VLIW DSP Subsystem at up to 600 MHz ·Fully Object-Code Compatible With C67x+ and C64x+Cores
·32KB of L1 Program Memory
·32KB of L1 Data Memory
·1024KB of L2 Configurable as L2 RAM or Cache
·ErrorDetection for L1 Program Memory
·ECC for L1 Data Memory
·ECC for L2 Data Memory
·Industrial Subsystem:
·Up to Two Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS), Each Supports: ·Two Programmable Real-Time Units (PRUs) With Enhanced Multiplier andAccumulator, Each PRU Supports:·16KB of Program Memory WithECC
·8KB of Data Memory With ECC
·CRC32 and CRC16 HardwareAccelerator
·20 × Enhanced GPIO
·Serial Capture Unit (SCU),Supporting Direct Connection, 16-bit Parallel Capture, 28-bit Shift, MII_RT, EnDat 2.2 Protocol andSigma-Delta Demodulation
·Scratch Pad and XFR DirectConnect

·64KB of General-Purpose MemoryWith ECC
·One Ethernet MII_RT Module with Two MII Ports Configurable for ConnectionWith Each PRU; Support Multiple Industrial Communication Protocols
·IndustrialEthernet Peripheral (IEP) to Manage and Generate Industrial EthernetFunctions
·Built-In Universal Asynchronous Receiver and Transmitter (UART)16550, With a Dedicated 192-MHz Clock to Support 12-MbpsPROFIBUS®
·Built-In Industrial Ethernet 64-BitTimer
·Built-In Enhanced Capture Module(eCAP)

·Memory Subsystem:
·Multicore Shared Memory Controller (MSMC) With 1024KB of Shared L2 RAM·ProvidesHigh-Performance Interconnect to Internal Shared SRAM and DDR EMIF for Both ARM A15 and C66x Access
·Supports ARM I/O Coherency Where ARM A15 is Cache Coherent to Other SystemMasters Accessing the MSMC-SRAM or DDR EMIF
·Supports ECC on SRAM

·Up to 36-Bit DDR External Memory Interface (EMIF)·SupportsDDR3L at up to 800MT/s
·Supports 4-GB Memory Address Range
·Supports 32-BitSDRAM Data Bus With 4-bit ECC
· Supports 16-Bit and32-Bit SDRAM Data Bus Without ECC

·General-Purpose Memory Controller (GPMC)·Flexible 8- and 16-Bit Asynchronous Memory Interface With up to FourChip Selects
·Supports NAND, NOR, Muxed-NOR, SRAM
·Supports General-Purpose Memory-Port Expansion With the FollowingModes:·Asynchronous Read and Write Access
·Asynchronous ReadPage Access (4-, 8-, 16-Word16)
·Synchronous Read and WriteAccess
·Synchronous Read Burst Access Without Wrap Capability (4-, 8-,16-Word16)

·Upto 16-Bit ECC Support for NAND Flash Using BCH Code (t = 4, 8, or 16) or HammingCode

·Error Location Module (ELM) ·Used With the GPMC to Locate Addresses of Data Errors From SyndromePolynomials Generated Using a BCH Algorithm
·Supports 4-Bit, 8-Bit and 16-Bitper 512-Byte Block Error Location Based on BCH Algorithms
·Provides ECCCalculation (Up to 16 bits) for NAND Support

·Network Subsystem (NSS):
·Ethernet MAC Subsystem (EMAC) ·One-Port Gigabit Ethernet: RMII, MII, RGMII
·Supports10-, 100-, 1000-Mbps Full Duplex
·Supports 10-, 100-Mbps HalfDuplex
·Supports Ethernet Audio Video Bridging(eAVB)
·Maximum Frame Size 2016 Bytes (2020 Bytes WithVLAN)
·Eight Priority Level QOS Support (802.1p)
·IEEE 1588v2(2008 Annex D, Annex E, and Annex F) to Facilitate Audio Video Bridging 802.1AS Precision Time Protocol
·CPTS Module With Timestamping Support for IEEE 1588v2
·DSCP Priority Mapping (IPv4 and IPv6)
·MDIO Module for PHYManagement
·Enhanced Statistics Collection
·Navigator Subsystem (NAVSS) ·Built-In Packet DMA Controller for Optimized NetworkProcessing
·Built-In Queue Manager (QM) for Optimized NetworkProcessing·Supports up to 128 Queues
·2048 Buffers Supported inInternal Queue RAM


·Crypto Engine (SA) Supports: ·Crypto Function Library for AES, DES, 3DES, SHA1,MD5, SHA2-224 and SHA2-256 Operations
·Block Data Encryption Supported Through Hardware Cores·AES With 128-, 192-, and 256-Bit Key Supports
·DESand 3DES With 1, 2, or 3 Different Key Support

·Programmable Mode Control Engine (MCE)
·Public KeyAccelerator (PKA) With Elliptic Curve Cryptography
·Elliptic Curve Diffie–Hellman (ECDH) Based KeyExchange and Digital Signature (ECDSA) Applications
·Authentication for SHA1,MD5, SHA2-224 and SHA2-256
·Keyed HMAC Operation Through HardwareCore
·TrueRandom Number Generator (TRNG)
·Display Subsystem:
·Supports One Video Pipe With In-Loop Scaling, Color Space
·Conversion and Background Color Overlay
·Input Data Format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8
·Supported Display Interfaces: ·MIPI® DPI 2.0 Parallel Interface
·RFBI (MIPI-DBI2.0) up to QVGA at 30fps
·BT.656 4:2:2
·BT.1120 4:2:2 up to1920 × 1080 at 30fps

·In-Loop Scaling Capability
·LCD Display Interface Supports: ·Active Matrix (TFT)
·Passive Matrix(STN)
·Grayscale
·TDM
·AC BiasControl
·Dither
·CPR

·High-Speed Serial Interfaces:
·PCI Express® 2.0 Port with Integrated PHY: ·Single Lane Gen2-Compliant Port
·Root Complex (RC) and EndPoint (EP) Modes
·Up to Two USB 2.0 High-Speed Dual-Role Ports With Integrated PHYs, Support: ·Dual-role-device (DRD) Capability With:·USB 2.0 Peripheral (or Device) at HS (480Mbps) and FS (12Mbps) Speeds
·USB 2.0 Host at HS(480Mbps), FS (12Mbps), and LS (1.5Mbps) Speeds
·USB 2.0 Static Peripheral and Static Host Operations
·xHCI Controller With the FollowingFeatures:·Compatible to the xHCI Specification (revision 1.1) in Host Mode
·All Modes of Transfer (Control, Bulk, Interrupt, andIsochronous)
·15 Transmit (TX), 15 Receive (RX) Endpoints (EPs), and OneBidirectional EP0 Endpoint


·Flash Media Interfaces:
·QSPI™ With XIP and up to Four Chip Selects, Supports: · Memory-Mapped Direct Mode of Operation for Performing FLASH Data Transfersand Executing Code From FLASH Memory (XIP)
·Supports up to 96MHz
· Internal SRAM Buffer With ECC
·High Speed Read Data Capture Mechanism

·Two Multimedia Card (MMC) and Secure Digital (SD) Ports ·Supports JEDEC JESD84 v4.5-A441 and SD3.0 Physical Layer With SDA3.00Standards
·MMC0 Supports 3.3-V I/O for: ·SD DS and HS Mode
·eMMC Mode HS-SDR and DDRup to 48 MHz

·MMC1 Supports 1.8-V I/O Modes for eMMC, IncludingHS-SDR and DDR at up to 48 MHz With 4- and 8-Bit Bus Width

·Audio Peripherals:
·Three Multichannel Audio Serial Port (McASP) Peripherals·Transmit and ReceiveClocks up to 50 MHz
·Two Independent Clock Zones and Independent Transmit andReceive Clocks per McASP
·Up to 16-, 10-, 6-Serial Data Pins for McASP0, McASP1,and McASP2, Respectively
·Supports TDM, I2S, and SimilarFormats
·Supports DIT Mode
·Built-In FIFO Buffers forOptimized System Traffic

·Multichannel Buffered Serial Port (McBSP)·Transmit and Receive Clocks up to 50MHz
·Two Clock Zones and Two Serial-Data Pins
·Supports TDM,I2S, and Similar Formats

·Automotive Peripherals:
·Two Controller Area Network (CAN) Ports ·Supports CAN v2.0 Part A, B (ISO 11898-1) Protocol
·BitRates up to 1 Mbps
·Dual Clock Source
·ECC Protection for MessageRAM

·One Media Local Bus (MLB)·Supports Both 3-Pin (Up to MOST50, 1024 × Fs) and 6-Pin (Up toMOST150, 2048 × Fs) Versions of MediaLB® Physical Layer Specification v4.2
·SupportsAll Types of Data Transfer Over 64 Logical Channels (Synchronous Stream, Isochronous, AsynchronousPacket, Control Message)
·Supports 3-Wire MOST 150Protocol

·Real-Time Control Interfaces:
·Six Enhanced High Resolution Pulse Width Modulation (eHRPWM) Modules, Each Counter Supports: · Dedicated 16-Bit Time-Base With Period and FrequencyControl
·Two Independent PWM Outputs With Single EdgeOperation
·Two Independent PWM Outputs With Dual-Edge SymmetricOperation
·One Independent PWM Output With Dual-Edge AsymmetricOperation

·Two 32-Bit Enhanced Capture Modules (eCAP): ·Supports One Capture Input or One Auxiliary PWM Output Configuration Options
·4-Event Time-Stamp Registers (Each 32-Bits)
·Interrupt onEither of the Four Events

·Three 32-Bit Enhanced Quadrature Pulse Encoder Modules (eQEP), Each Supports: ·Quadrature Decoding
·Position Counter and Control Unitfor Position Measurement
·Unit Time Base for Speed and FrequencyMeasurement

·General Connectivity:
·Three Inter-Integrated Circuit (I2C) Interfaces, Each Supports:·Standard (up to 100 kHz) and Fast (up to 400 kHz) Modes
·7-Bit AddressingMode
·Supports EEPROM Size Up to4Mbit

·Four Serial Peripheral Interfaces (SPI), Each Supports:·Operates at up to 50 MHz in Master Mode and 25 MHz in SlaveMode
·Two Chip Selects

·Three UART Interfaces·All UARTs are 16C750-Compatible and Operate at Up to 3MBaud
·UART0 Supports 8 Pins With Full Modem Control, With DSR, DTR, DCD, and RISignals
·UART1 and UART2 are 4-PinInterfaces

·General-Purpose I/O (GPIO)·Up to 212 GPIOs Muxed With Other Interfaces
·Canbe Configured as Interrupt Pins

·Timers and Miscellaneous Modules:
·Seven 64-Bit Timers:· Two 64-BitTimers Dedicated to ARM A15 and DSP Cores (One Timer per Core)·Watchdog and General-Purpose (GP)

·Four 64-Bit Timers are Shared for GeneralPurposes
·Each 64-Bit Timer Can be Configured as TwoIndividual 32-Bit Timers
·One 64-Bit Timer Dedicated forPMMC
·Two Timers Input/Output Pin Pairs

· Interprocessor Communication With: ·Message Manager to Facilitate Multiprocessor Access to the PMMC: ·Provides HardwareAcceleration for Pushing and Popping Messages to/from Logical Queues
· Supports Up to 64 Queues and 128Messages

·Semaphore Module With Up to 64 IndependentSemaphores and 16 Masters (device cores)

·EDMA With 128 (2 × 64) Channels and 1024 (2 × 512) PaRAM Entries
·Keystone II System on Chip (SoC) Architecture:
·Security · Supports General-Purpose (GP) and High-Secure (HS)Devices
·Supports Secure Boot
·SupportsCustomer Secondary Keys
·4KB ofOne-Time Programmable (OTP) ROM for Customer Keys

·Power Management ·Integrated Power ManagementMicrocontroller (PMMC) Technology

·Supports Primary Boot From UART, I2C, SPI, GPMC, SD or eMMC, USB Device Firmware Upgrade v1.1, PCIe®, and Ethernet Interfaces
·Keystone II Debug Architecture With Integrated ARM CoreSight™ Support and Trace Capability
·Operating Temperature (TJ):
·–40°C to 125°C (Automotive)
·–40°C to 105°C (Extended)
·0°C to 90°C (Commercial)
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