6116数据手册Renesas中文资料规格书

描述 Description

The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.

特性 Features

High-speed access and chip select times – Military: 20/25/35/45/55/70/90/120/150ns (max.) – Industrial: 20/25ns (max.) – Commercial: 15/20/25ns (max.)
Low-power consumption
Battery backup operation – 2V data retention voltage (LA version only)
Produced with advanced CMOS high-performance technology
CMOS process virtually eliminates alpha particle soft-error rates
Input and output directly TTL-compatible
Static operation: no clocks or refresh required
Available in ceramic 24-pin DIP, ceramic and plastic 24-pin Thin Dip and 24-pin SOIC packages
Military product compliant to MIL-STD-833, Class B