5T9950A中文资料2.5V Programmable Skew PLL Clock Driver数据手册Renesas规格书

描述 Description

The 5T9950 is a high fanout 2.5V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The 5T9950 has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are synchronously disabled. The LOCK output asserts to indicate when Phase Lock has been achieved. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The 5T9950 has LVTTL outputs with 12mA balanced drive outputs.

特性 Features

Ref input is 3.3V tolerant
4 pairs of programmable skew outputs
Low skew: 185ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization: Excellent for DSP applications
Synchronous output enable
Input frequency:– Std: 6MHz to 160MHz– A: 6MHz to 200MHz
Output frequency:– Std: 6MHz to 160MHz– A: 6MHz to 200MHz
2x, 4x, 1/2, and 1/4 outputs
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Standard and A speed grades
Available in TQFP package
Not Recommended for New Design