FEATURES:

• Optimized for 2.5V LVTTL

• Guaranteed Low Skew < 25ps (max)

• Very low duty cycle distortion < 300 (max)

• High speed propagation delay < 1.8ns. (max)

• Up to 200MHz operation

• Very low CMOS power levels

• Hot insertable and over-voltage tolerant inputs

• 1:5 fanout buffer

• 2.5V VDD

• Available in TSSOP package

• For New Designs use functional replacement 8L30110

DESCRIPTION:

The 5T9050 2.5V single data rate (SDR) clock buffer is a single-ended input

to fi ve single-ended outputs buffer built on advanced metal CMOS technology.

The SDR clock buffer fanout from a single input to fi ve single-ended outputs

reduces the loading on the preceding driver and provides an effi cient clock

distribution network. Multiple power and grounds reduce noise.

5T9050属于集成电路（IC） > 时钟缓冲器，驱动器。瑞萨科技有限公司制造生产的5T9050时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。