5P49V6967集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

描述 Description

The 5P49V6967 is a programmable clock generator intended for

high-performance consumer, networking, industrial, computing,

and data-communications applications. This is Renesas’ sixth

generation of programmable clock technology (VersaClock 6E).

The frequencies are generated from a single reference clock. The

reference clock can originate from one of the two redundant clock

inputs. A glitchless manual switchover function allows one of the

redundant clocks to be selected during normal operation.

Two select pins allow up to four different configurations to be

programmed and may be used for different operating modes

特性 Features

 Flexible 1.8V, 2.5V, 3.3V power rails

 High-performance, low phase noise PLL, < 0.5ps RMS typical

phase jitter on outputs

 Four banks of internal OTP memory

— In-system or factory programmable

 I

2C serial programming interface

— 0xD0 or 0xD4 I

2C address options allow multiple devices

configured in a same system.

 Reference LVCMOS output clock

 Three Universal configurable outputs (OUT1, 2, 4):

— Differential (LVPECL, LVDS, or HCSL)

1kHz to 350MHz

— Two single-ended (in-phase or 180 degrees out of phase)

1kHz to 200MHz

— I/O VDDs can be mixed and matched, supporting 1.8V

(LVDS and LVCMOS), 2.5V, or 3.3V

— Independent spread spectrum on each output pair

 Four additional LPHCSL outputs (OUT 3, 5, 6, 7)

— 1.8V low power supply

— 1kHz to 200MHz

 Programmable output enable or power-down mode

 Available in 5 × 5 mm 40-VFQFPN package

 -40° to +85°C industrial temperature operation