5P49V5929集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

特性 Features

• Generates up to four independent output frequencies

• High performance, low phase noise PLL, <0.7 ps RMS

typical phase jitter on outputs

• Four fractional output dividers (FODs)

• Independent Spread Spectrum capability on each output

pair

• Four banks of internal non-volatile in-system

programmable or factory programmable OTP memory

• I2C serial programming interface

• Nine LVCMOS outputs, including one reference output

• I/O Standards:

– Single-ended I/Os: 1.8V to 3.3V LVCMOS

• Input frequency ranges:

– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to

200MHz

– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,

CLKINB) – 1MHz to 200MHz

– Crystal frequency range: 8MHz to 40MHz

• Output frequency ranges:

– LVCMOS Clock Outputs – 1MHz to 200MHz

• Individually selectable output voltage (1.8V, 2.5V, 3.3V) for

each output pair

• Redundant clock inputs with manual switchover

• Programmable loop bandwidth

• Programmable slew rate control

• Programmable crystal load capacitance

• Individual output enable/disable

• Power-down mode

• 1.8V, 2.5V or 3.3V core VDDD, VDDA

• Available in 24-pin VFQFPN 4mm x 4mm package

• -40° to +85°C industrial temperature operation