56F8036中文资料16-bit Digital Signal Controllers数据手册恩XP规格书

描述 Description

• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified, C-efficient architecture
• 64KB (32K x 16) Program Flash
• 8KB (4K x 16) Unified Data/Program RAM
• One 6-channel PWM module clocked at up to 96MHz
• Two independent 5-channel 12-bit high-speed Analog-to-Digital Converters (ADCs)
• Two internal 12-bit Digital-to-Analog Converters (DACs)
• Two Analog Comparators
• Three Programmable Interval Timers (PITs)
• One Queued Serial Communication Interface (QSCI) with LIN slave functionality
• One Queued Serial Peripheral Interface (QSPI)
• Freescale’s scalable controller area network (MSCAN) 2.0 A/B Module
• One 16-bit Quad Timer clocked at up to 96MHz
• One Inter-Integrated Circuit (I2C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging
• Up to 39 GPIO lines
• 48-pin LQFP Package