557-01中文资料PCI Express® GEN1 Clock Source数据手册Renesas规格书

描述 Description

The 557-01 is a clock chip designed for use in PCI Express® Cards as a clock source. It provides a pair of differential outputs at 100 MHz in a small 8-pin SOIC package. Using IDT's patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces HCSL (Host Clock Signal Level) differential outputs at 100 MHz clock frequency. LVDS signal levels can also be supported via an alternative termination scheme.

特性 Features

Supports PCI Express®TM HCSL Outputs 0.7 V current mode differential pair
Supports LVDS Output Levels
Packaged in 8-pin SOIC
RoHS 5 (green) or RoHS 6 (green and lead free) compliant packaging
Operating voltage of 3.3 V
Low power consumption
Input frequency of 25 MHz
Short term jitter 100 ps (peak-to-peak)
Output Enable via pin selection
Industrial temperature range available
For PCIe Gen2 applications, see the 5V41064
For PCIe Gen3 applications, see the 5V41234