Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

文件：118.08 Kbytes 页数：6 Pages

NSC

国半

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK

文件：240.11 Kbytes 页数：8 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK

文件：240.11 Kbytes 页数：8 Pages

TI

德州仪器

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The SN54/74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed sothat when the clock goes HIGH, the inputs are enabled and data will be accepted.The logic level of the J and K inputs may be allowed to change when the

文件：146.37 Kbytes 页数：4 Pages

Motorola

摩托罗拉