542MLF集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

描述 Description

The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide by two of the other.

特性 Features

• 8-pin SOIC package

• Available in RoHS compliant package

• IDT’s lowest cost clock divider

• Low skew (500 ps) outputs. One is /2 of the other

• Easy to use with other generators and buffers

• Input clock frequency up to 156 MHz

• Output clock duty cycle of 45/55

• Power-down turns off chip

• Output Enable

• Advanced, low-power CMOS process

• Operating voltage of 3.3 V or 5 V

• Does not degrade phase noise - no PLL

• Available in industrial and commercial temperature

ranges