CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

文件：171.43 Kbytes 页数：6 Pages

IDT

丝印：542MLF；Package：SOIC；CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

文件：119.34 Kbytes 页数：6 Pages

IDT

Package：8-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：IC CLK BUFFER 1:2 156MHZ 8SOIC

RENESAS

瑞萨

UHF power MOS transistor

DESCRIPTION Silicon N-channel enhancement mode vertical D-MOS transistor designed for large signal amplifier applications in the UHF frequency range. The transistor is encapsulated in a 6-lead, SOT171 flange envelope, with a ceramic cap. All leads are isolated from the flange. FEATURES • High

文件：101.69 Kbytes 页数：12 Pages

PHI

PHI

8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS

文件：169.07 Kbytes 页数：11 Pages

TI

德州仪器

8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS

文件：169.07 Kbytes 页数：11 Pages

TI

德州仪器