丝印：54；Package：SOT1089；Low-power D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：349.69 Kbytes 页数：26 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：54；Package：SOT1116；Low-power D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：349.69 Kbytes 页数：26 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：54；Package：SOT1203；Low-power D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：349.69 Kbytes 页数：26 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：54；Package：SOT1233-2；Low-power D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：349.69 Kbytes 页数：26 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：54；Package：SOT-523；Digital Transistor

Features - Epitaxial planar die construction. - Built-in biasing resistors, R1≠R2. - AEC-Q101 Qualified.

文件：482.58 Kbytes 页数：5 Pages

COMCHIP

典琦

丝印：54；DIGITAL TRANSISTOR

Features 1) Built-In Biasing Resistors, R1 = R2 = 10kΩ 2) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see inner circuit) . 3) Only the on/off conditions need to be set for operation, making the circuit design e

文件：704.49 Kbytes 页数：9 Pages

ROHM

罗姆

丝印：54；Package：SOT-416；PNP -100mA -50V Digital Transistor

Digital transistors (built-in resistors)

文件：1.8274 Mbytes 页数：14 Pages

ROHM

罗姆

丝印：54；Package：SOT-416；Digital transistors (built-in resistors)

Features 1) Built-In Biasing Resistors 2) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see inner circuit) . 3) The bias resistors consist of thin-film resistors with complete isolation to allow negative biasing

文件：89.21 Kbytes 页数：4 Pages

ROHM

罗姆

丝印：54；Package：SOT-416；PNP -100mA -50V Digital Transistor (Bias Resistor Built-in Transistor)

Features 1) Built-In Biasing Resistors, R1 = 10kΩ, R2 = 47kΩ 2) Built-in bias resistors enable the configuration of 　an inverter circuit without connecting external 　input resistors (see inner circuit) . 3) Only the on/off conditions need to be set 　for operation, making the circuit design e

文件：1.39675 Mbytes 页数：8 Pages

ROHM

罗姆

丝印：54；Package：SOT-490；PNP -100mA -50V Digital Transistor

Digital transistors (built-in resistors)

文件：1.8274 Mbytes 页数：14 Pages

ROHM

罗姆