524S中文资料Low Skew 1 to 4 Clock Buffer数据手册Renesas规格书

描述 Description

The 524S is a low skew, single input to four output, LVCMOS clock buffer. The 524S has best in class additive phase Jitter of sub 50 fsec.

特性 Features

• Low additive phase jitter RMS: 50fs
• Low cost clock buffer
• ICLK is PDT and may be driven before VDD is applied
• Input / Output clock frequency up to 200MHz
• Ideal for networking clocks
• Advanced, low power CMOS process
• Extended temperature range (-40°C to +105°C)