501A中文资料PLL Clock Multiplier数据手册Renesas规格书

描述 Description

The 501A is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. It is designed to replace crystal oscillators in most electronic systems. Using Phase-Locked Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 200 MHz. Stored in the chip's ROM is the ability to generate nine different multiplication factors, allowing one chip to output many common frequencies (see table on page 2). The device also has an output enable pin which tri-states the clock output when the OE pin is taken low. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined or guaranteed. For applications which require defined input to output skew, use the 570B.

特性 Features

·Packaged as 8-pin SOIC (Pb-free) or die
·IDT's lowest cost PLL clock
·Zero ppm multiplication error
·Input crystal frequency of up to 27 MHz
·Input clock frequency of up to 50 MHz
·Output clock frequencies up to 200 MHz
·Extremely low jitter of 25 ps (one sigma)
·Compatible with all popular CPUs
·Duty cycle of 45/55 up to 200 MHz
·Nine selectable frequencies
·Operating voltage of 3.3 V
·Tri-state output for board level testing
·25 mA drive capability at TTL levels
·Ideal for oscillator replacement
·Optimized for output frequencies of up to 200 MHz (166 MHz maximum for industrial temperature version)
·Industrial temperature version available
·Advanced, low power CMOS process