4S204BIL中文资料LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER数据手册Renesas规格书

描述 Description

GENERAL DESCRIPTION
The ICS854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer and a member of the HiPerClockS™family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels. With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels. The ICS854S204I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and bank skew characteristics make the ICS854S204I ideal for those clock distribution applications demanding well defined performance and repeatability.FEATURES
• Two programmable differential LVDS or LVPECL output banks
• Two differential clock input pairs
• PCLKx, nPCLKx pairs can accept the following differential
   input levels: LVDS, LVPECL, SSTL, CML
• Maximum output frequency: 3GHz
• Translates any single ended input signal to LVDS levels
   with resistor bias on nPCLKx inputs
• Output skew: 15ps (maximum)
• Bank skew: 15ps (maximum)
• Propagation delay: 500ps (maximum)
• Additive phase jitter, RMS: 0.15ps (typical)
• Full 3.3V or 2.5V power supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package

特性 Features

• Two programmable differential LVDS or LVPECL output banks
• Two differential clock input pairs
• PCLKx, nPCLKx pairs can accept the following differential
   input levels: LVDS, LVPECL, SSTL, CML
• Maximum output frequency: 3GHz
• Translates any single ended input signal to LVDS levels
   with resistor bias on nPCLKx inputs
• Output skew: 15ps (maximum)
• Bank skew: 15ps (maximum)
• Propagation delay: 500ps (maximum)
• Additive phase jitter, RMS: 0.15ps (typical)
• Full 3.3V or 2.5V power supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package