丝印：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

Features • Two programmable differential LVDS or LVPECL output banks • Two differential clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML • Maximum output frequency: 3GHz • Translates any single ended input signal to LVDS leve

文件：1.42469 Mbytes 页数：23 Pages

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瑞萨

丝印：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

Features • Two programmable differential LVDS or LVPECL output banks • Two differential clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML • Maximum output frequency: 3GHz • Translates any single ended input signal to LVDS leve

文件：1.42469 Mbytes 页数：23 Pages

RENESAS

瑞萨

丝印：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

文件：1.42533 Mbytes 页数：23 Pages

IDT

丝印：4S204BIL；Package：TSSOP；Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

文件：1.42533 Mbytes 页数：23 Pages

IDT

LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER

GENERAL DESCRIPTION\nThe ICS854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer and a member of the HiPerClockS™family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels. W • Two programmable differential LVDS or LVPECL output banks\n• Two differential clock input pairs\n• PCLKx, nPCLKx pairs can accept the following differential\n   input levels: LVDS, LVPECL, SSTL, CML\n• Maximum output frequency: 3GHz\n• Translates any single ended input signal to LVDS levels\n   wi;

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