23S08-1DCG集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

FEATURES:

• Phase-Lock Loop Clock Distribution for Applications ranging

from 10MHz to 133MHz operating frequency

• Distributes one clock input to two banks of four outputs

• Separate output enable for each output bank

• External feedback (FBK) pin is used to synchronize the outputs

to the clock input

• Output Skew <200 ps

• Low jitter <200 ps cycle-to-cycle

• 1x, 2x, 4x output options (see table):

– IDT23S08-1 1x

– IDT23S08-2 1x, 2x

– IDT23S08-3 2x, 4x

– IDT23S08-4 2x

– IDT23S08-1H, -2H, and -5H for High Drive

• No external RC network required

• Operates at 3.3V VDD

• Spread spectrum compatible

• Available in SOIC and TSSOP packages