23S05T-1DC8中文资料瑞萨数据手册PDF规格书

FEATURES:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five outputs

• Zero Input-Output Delay

• Output Skew < 250ps

• Low jitter <200 ps cycle-to-cycle

• No external RC network required

• Operates at 2.5V VDD

• Power down mode

• Spread spectrum compatible

• Available in SOIC package

NOTE: EOL for non-green parts to occur on 5/13/10 per

PDN U-09-01