11C91数据手册TI中文资料规格书

描述 Description

General Description
The 11C90 and 11C91 are high-speed prescalers designed specifically for communication and instrumentation applications. All discussions and examples in this data sheet are applicable to the 11C91 as well as the 11C90.
The 11C90 will divide by 10 or 11 and the 11C91 by 5 or 6, both over a frequency range from DC to typically 650 MHz. The division ratio is controlled by the Mode Control. The divide-by-10 or -11 capability allows the use of pulse swallowing techniques to control high-speed counting modulos by lower-speed circuits. The 11C90 may be used with either ECL or TTL power supplies.
In addition to the ECL outputs Q and Q, the 11C90 contains an ECL-to-TTL converter and a TTL output. The TTL output operates from the same VCC and VEE levels as the counter, but a separate pin is used for the TTL circuit VEE. This minimizes noise coupling when the TTL output switches and also allows power consumption to be reduced by leaving the separate VEE pin open if the TTL output is not used. To facilitate capacitive coupling of the clock signal, a 400X resistor (VREF) is connected internally to the VBB reference. Connecting this resistor to the Clock Pulse input (CP) automatically centers the input about the switching threshold. Maximum frequency operation is achieved with a 50% duty cycle.
Each of the Mode Control inputs is connected to an internal 2 kX resistor with the other end uncommitted (RM1 and RM2). An M input can be driven from a TTL circuit operating from the same VCC by connecting the free end of the associated 2 kX resistor to VCCA. When an M input is driven from the ECL circuit, the 2 kX resistor can be left open or, if required, can be connected to VEE to act as a pull-down resistor.