ZL671数据手册Microchip中文资料规格书

描述 Description

The ZL30671 offers one DPLL channel of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, these devices offer new and improved features for 5G transport and wireless infrastructure equipment.  Each device integrates all features required by a timing card PLL and line card PLL. High integration along with ultra-low jitter make these devices ideal for use in chassis based systems with active and redundant timing cards as well as in single board (“pizza box”) applications where a timing device needs to have features of both a timing and a line card PLL.

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特性 Features

Key Features
• Up to three independent clock channels
• Precise phase/frequency measurement and tuning lower system latency to meet 4G LTE, 5G & Wireless Infrastructure
• Ultra-fast lock to GPS/GNSS and 1PPS for faster power-up time for 4G LTE, 5G & Wireless Infrastructure
• Precise chip-to-chip time interfaces use less backplane traces for 1PPS distribution for chassis systems
• Split oscillator option lowers cost, lowers jitter, and provides redundancy
• Fully compliant to EEC (G.8262), SEC (G.813), GR-253 SMC and GR-1244 Stratum 3/3E
• Excellent jitter performance of