ZL30683中文资料Network Synchronization数据手册Microchip规格书

描述 Description

The ZL30683 offers three DPLL channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, these devices offer new and improved features for 5G transport and wireless infrastructure equipment.  Each device integrates all features required by line card PLL. High integration along with ultra-low jitter make these devices ideal for use in frequency translation from backplane clock to frequencies required by PHY devices, jitter filtering, and holdover in case both active and redundant timing cards fail.

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特性 Features

Key Features
• Three independent DPLL channels
• Precise phase/frequency measurement and tuning lower system latency to meet 4G LTE, 5G & Wireless Infrastructure
• Precise chip-to-chip time interfaces use less backplane traces for 1PPS distribution for chassis systems
• Split oscillator option lowers cost, lowers jitter, and provides redundancy
• Excellent jitter performance of

简介

ZL30683属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30683应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。