YSS932中文资料YAMAHA数据手册PDF规格书

OUTLINE

YSS932 is one chip LSI consisting of three built-in blocks : SPDIF receiver (DIR), Dolby Digital (AC-3) / Pro Logic II & DTS decoder (Main DSP) and programmable sound fields processing DSP (Sub DSP). The Sub DSP is capable of realizing various sound fields, such as virtual surround by down-loading the program and coefficient from outside.

FEATURES

[DIR Block ]

•Sampling frequency: Two ranges are available including; 32k to 48kHz (normal rate) and 64k to 96kHz (double rate).

•Provides master clock, 256fs, to DAC, ADC and the other peripheral devices. The clock output can be

controlled with various modes determined by register settings.

•Has a pin that indicates the double rate operation.

•Every channel status and user data can beread through the microprocessor interface.

•Has an output pin for interrupt that is activated by changing of the status information.

•Internal operation frequency: 25MHz

[Main DSP Block ]

•Dolby Digital (AC-3) / Pro Logic II and DTS decode.

•High quality internal 24 bit DSP.

•No external memory is required. (Memory for the center and surround channel signal delay is included.)

•AC-3 Karaoke mode.

•Supports compression mode at AC-3 / DTS decoding.

•Included de-emphasis filter for the PCM signal.

•Pro Logic II decoding for Dolby Digital 2 channels decoded signal as well as ordinary PCM signal.

•Reads Dolby Digital / DTS decode information through the microprocessor interface.

•Internal operation frequency: 30MHz

[Sub DSP Block ]

•Capable of realizing various sound fields, such as simulation surround, output configuration and virtual

surround by downloading the programs from the microprocessor.

•Adoption of the 32 bit floating-point DSP assuring highly accurate processing.

•Up to 2.73 seconds delay at fs=48kHz achievable by adding DRAM or SRAM externally.

•Internal operation frequency: 30MHz

[Other Features ]

•Connectable to almost all ADC and DAC by making appropriate settings to the control register.

•Total of 16 general purpose input/output ports are provided.

•2 built-in PLL circuits for generation of operation clocks for DIR block and DSP blocks.

•Power supply voltage: 2 power sources (2.5V for core logic section and 3.3V for I/O section)

•Si-gate CMOS process

• 128SQFP (YSS932-S)