I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

文件：1.23645 Mbytes 页数：63 Pages

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艾科嘉

I2C/SPI UART with 128-Byte FIFO and Integrated Level Shifters

The XR20M1280¹ (M1280) is a single-channel I2C/SPI Universal Asynchronous Receiver and Transmitter (UART) with integrated level shifters and 128 bytes of transmit and receive FIFOs.\nFor flexibility in a mixed voltage environment, the M1280 has 4 VCC pins. There is a VCC pin for the core, a VCC pin ·Integrated Level Shifters on CPU interface, UART and GPIO signals\n·Selectable I2C/SPI bus interface\n·26MHz maximum SPI clock\n·24Mbps maximum UART data rate\n·Up to 16 GPIOs\n·128-Bytes TX and RX FIFOs\n·Programmable TX/RX trigger levels\n·TX/RX FIFO Level Counters\n·Independent TX/RX Baud Rate G;

MaxLinear

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I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

文件：1.23645 Mbytes 页数：63 Pages

EXAR

艾科嘉

I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

文件：1.23645 Mbytes 页数：63 Pages

EXAR

艾科嘉

I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

文件：1.23645 Mbytes 页数：63 Pages

EXAR

艾科嘉

I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

文件：1.23645 Mbytes 页数：63 Pages

EXAR

艾科嘉

I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

文件：1.23645 Mbytes 页数：63 Pages

EXAR

艾科嘉

I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

文件：1.23645 Mbytes 页数：63 Pages

EXAR

艾科嘉

I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

文件：1.23645 Mbytes 页数：63 Pages

EXAR

艾科嘉

Package：24-VFQFN 裸露焊盘；包装：卷带（TR） 功能：控制器 类别：集成电路（IC） 控制器 描述：IC UART I2C/SPI 128 BYTE 24QFN

MaxLinear, Inc.