DRA821 Jacinto™ Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper

文件：4.57573 Mbytes 页数：253 Pages

TI

德州仪器

DRA821 Jacinto™ Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper

文件：4.45374 Mbytes 页数：252 Pages

TI

德州仪器

KIT_XMC72_EVK XMC7200 evaluation kit guide

文件：2.08179 Mbytes 页数：59 Pages

INFINEON

英飞凌

XMC7000 microcontroller 32-bit Arm® Cortex®-M7 General description

Features • CPU subsystem - One or two 350-MHz 32-bit Arm® Cortex®-M7 CPUs, each with • Single-cycle multiply • Single/double-precision floating point unit (FPU) • 16-KB data cache, 16-KB instruction cache • Memory Protection Unit (MPU) • 16-KB instruction and 16-KB data Tightly-Coupled Memo

文件：2.10998 Mbytes 页数：189 Pages

INFINEON

英飞凌