WSF128K16-37HC中文资料WEDC数据手册PDF规格书

s (FLASH)

(FLASH

FEATURES

■ Access Times of 35ns (SRAM) and 70ns (FLASH)

■ Access Times of 70ns (SRAM) and 120ns (FLASH)

■ Packaging

• 66-pin, PGA Type, 1.075 inch square HIP, Hermetic Ceramic HIP (Package 400)

• 66-pin, PGA Type, 1.185 inch square HIP, Hermetic Ceramic HIP (Package 401)

• 68 lead, Hermetic CQFP (G1U), 22.4mm (0.880 inch) square (Package 519). Designed to fit JEDEC 68 lead 0.990” CQFJ footprint (Fig. 2)

■ 128Kx16 SRAM

■ 128Kx16 5V FLASH

■ Organized as 128Kx16 of SRAM and 128Kx16 of Flash Memory with separate Data Buses

■ Both blocks of memory are User Configurable as 256Kx8

■ Low Power CMOS

■ Commercial, Industrial and Military Temperature Ranges

■ TTL Compatible Inputs and Outputs

■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation

■ Weight

• WSF128K16-XHX - 13 grams typical

• WSF128K16-H1X - 13 grams typical

• WSF128K16-XG1UX - 5 grams typical

FLASH MEMORY FEATURES

■ 10,000 Erase/Program Cycles

■ Sector Architecture

• 8 equal size sectors of 16K bytes each

• Any combination of sectors can be concurrently erased.

Also supports full chip erase

■ 5 Volt Programming; 5V ± 10 Supply

■ Embedded Erase and Program Algorithms

■ Hardware Write Protection

■ Page Program Operation and Internal Program Control Time.