512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM

DESCRIPTION The WED2ZLRSP01S, Dual Independent Array, NBL-SSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the fi rst organized as a 512K x 32, and the second a 256

文件：350.39 Kbytes 页数：13 Pages

WEDC

512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM

DESCRIPTION The WED2ZLRSP01S, Dual Independent Array, NBL-SSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the fi rst organized as a 512K x 32, and the second a 256

文件：350.39 Kbytes 页数：13 Pages

WEDC

512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM

DESCRIPTION The WED2ZLRSP01S, Dual Independent Array, NBL-SSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the fi rst organized as a 512K x 32, and the second a 256

文件：350.39 Kbytes 页数：13 Pages

WEDC

512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM

DESCRIPTION The WED2ZLRSP01S, Dual Independent Array, NBL-SSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the fi rst organized as a 512K x 32, and the second a 256

文件：350.39 Kbytes 页数：13 Pages

WEDC

512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM

DESCRIPTION The WED2ZLRSP01S, Dual Independent Array, NBL-SSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the fi rst organized as a 512K x 32, and the second a 256

文件：350.39 Kbytes 页数：13 Pages

WEDC

512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM

DESCRIPTION The WED2ZLRSP01S, Dual Independent Array, NBL-SSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the fi rst organized as a 512K x 32, and the second a 256

文件：350.39 Kbytes 页数：13 Pages

WEDC

512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM

DESCRIPTION The WED2ZLRSP01S, Dual Independent Array, NBL-SSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the fi rst organized as a 512K x 32, and the second a 256

文件：350.39 Kbytes 页数：13 Pages

WEDC

512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM

DESCRIPTION The WED2ZLRSP01S, Dual Independent Array, NBL-SSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the fi rst organized as a 512K x 32, and the second a 256

文件：350.39 Kbytes 页数：13 Pages

WEDC

512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM

Microchip

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