WC32P020-XP2M中文资料16 32-Bit General-Purpose Data and Address Registers数据手册Microchip规格书

描述 Description

DESCRIPTION
The WC32P020 is a 32-bit implementation of the 68000 Family of microprocessors. Using HCMOS technology, the WC32P020 is implemented with 32-bit registers and data paths, 32-bit addresses, a powerful instruction set, and fl exible addressing modes.68020 FEATURES
■ Selection of Processor Speeds: 16.67, 20, 25 MHz
■ Military Temperature Range: -55°C to +125°C
■ Packaging
  
• 114 pin Ceramic PGA (P2)
  
• 132 lead Ceramic Quad Flatpack, CQFP (Q2)
■ Object-code compatible with earlier 68000 Microprocessors
■ Addressing mode extensions for enhanced support of high-level languages
■ Bit Field Data Type Accelerates Bit-Oriented Applications–i.e., Video Graphics
■ Fast On-Chip Instruction Cache Speeds Instructions and Improves Bus Bandwidth
■ Coprocessor Interface to Companion 32-Bit Peripherals–the 68881 and 68882 Floating-Point Coprocessors and the 68851 Paged Memory Management Unit
■ Pipelined Architecture with High Degree of Internal Parallelism allowing Multiple Instructions to be executed concurrently
■ High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32-Bits
■ Dynamic Bus Sizing Effi ciently Supports 8-/16-/32-Bit Memories and Peripherals
■ Full Support of Virtual Memory and Virtual Machine
■ 16 32-Bit General-Purpose Data and Address Registers
■ Two 32-Bit Supervisor Stack Pointers and Five Special-Purpose Control Registers
■ 18 Addressing Modes and 7 Data Types
■ 4 GigaByte Direct Addressing Range

特性 Features

■ Selection of Processor Speeds: 16.67, 20, 25 MHz
■ Military Temperature Range: -55°C to +125°C
■ Packaging
  
• 114 pin Ceramic PGA (P2)
  
• 132 lead Ceramic Quad Flatpack, CQFP (Q2)
■ Object-code compatible with earlier 68000 Microprocessors
■ Addressing mode extensions for enhanced support of high-level languages
■ Bit Field Data Type Accelerates Bit-Oriented Applications–i.e., Video Graphics
■ Fast On-Chip Instruction Cache Speeds Instructions and Improves Bus Bandwidth
■ Coprocessor Interface to Companion 32-Bit Peripherals–the 68881 and 68882 Floating-Point Coprocessors and the 68851 Paged Memory Management Unit
■ Pipelined Architecture with High Degree of Internal Parallelism allowing Multiple Instructions to be executed concurrently
■ High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32-Bits
■ Dynamic Bus Sizing Effi ciently Supports 8-/16-/32-Bit Memories and Peripherals
■ Full Support of Virtual Memory and Virtual Machine
■ 16 32-Bit General-Purpose Data and Address Registers
■ Two 32-Bit Supervisor Stack Pointers and Five Special-Purpose Control Registers
■ 18 Addressing Modes and 7 Data Types
■ 4 GigaByte Direct Addressing Range