W7500数据手册集成电路（IC）的模块规格书PDF

描述 Description

The IOP (Internet Offload Processor) W7500  is the one-chip solution which integrates an ARM Cortex-M0, 128KB Flash and hardwired TCP/IP core for various embedded application platform especially requiring ‘Internet of things’.
The TCP/IP core is a market-proven hardwired TCP/IP stack with an integrated Ethernet MAC. The Hardwired TCP/IP stack supports the TCP, UDP, IPv4, ICMP, ARP, IGMP and PPPoE which has been used in various applications for years. W7500 suits best for users who need Internet connectivity for application.

特性 Features

ARM Cortex-M0●48MHz maximum frequency
Hardwired TCP/IP Core●8 Sockets
●SRAM for socket: Max. 32KB
●MII (Medium-Independent Interface)
Memories●Flash: 128 KB
●SRAM: 16KB to 48 KB ( Min 16KB available if 32KB socket buffer is used, Max 48KB available if no socket buffer is used)
●ROM for boot code: 6KB
Clock, reset and supply management●POR (Power-On Reset)
●Internal Voltage Regulator : 3.3V to 1.5V
●8-to-24MHz external crystal oscillator
●Internal 8MHz RC Oscillator
●PLL for CPU clock
ADC● 12bit, 8ch, 1Msps
DMA●6-channel DMA controller
●Peripheral supported: UARTs, SPIs
GPIO●53 I/Os (16 IO x 3ea, 5 IO x 1ea)
Debug mode●Serial Wire Debug (SWD)
Timer/PWM●1 Watchdog (32-bit down-counter)
●4 Timers (32-bit or 16-bit down-counter)
●8 PWMs (32-bit counter/timers with programmable 6-bit prescaler)
Communication Interfaces●3 UART (2 UARTs with FIFO and Flow Control, 1 simple UART)
●2 SPI
●2 I2C (Master/Slave, Fast-mode (400 kbps))
Crypto●1 RNG (Random Number Generator): 32-bit random number
Package : 64 TQFP (7×7 mm)

简介

W7500属于集成电路（IC）的模块。由制造生产的W7500模块端子块接口模块产品以分支或分线能力发挥互连功能，可用于方便地从高密度互连形式（例如 D-sub 或矩形连接器）转换为更易维护的低密度形式之一，例如一组端子块。这样，通过允许在控制设备与便于访问信号的维护或安装点之间使用高密度电缆，则可以简化工业控制系统中的安装和维护任务。