W25X40L中文资料华邦电子数据手册PDF规格书

GENERAL DESCRIPTION

The W25X10L (1M-bit), W25X20L (2M-bit), W25X40L (4M-bit) and W25X80L (8M-bit) Serial Flash memories provide a storage solution for systems with limited space, pins and power. The 25X series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code download applications as well as storing voice, text and data. The devices operate on a single 2.5V ( a range of 2.3V to 3.3V) power supply with current consumption as low as 5mA active and 1µA for power-down. All devices are offered in space-saving packages.

The W25X10L/20L/40L/80L array is organized into 512/1024/2048/4096 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time using the Page Program instruction. Pages can be erased in groups of 16 (sector erase), groups of 256 (block erase) or the entire chip (chip erase). The W25X10L/20L/40L/80L has 32/64/128/256 erasable sectors and 2/4/8/16 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.)

The W25X10L/20L/40L/80L supports the standard Serial Peripheral Interface (SPI), and a high performance dual output SPI and low voltage operation using four pins: Serial Clock, Chip Select, Serial Data I/O and Serial Data Out. SPI clock frequencies of up to 40MHz are supported allowing equivalent clock rates of 80MHz when using the Fast Read Dual Output instruction. These transfer rates are comparable to those of 8 and 16-bit Parallel Flash memories.

A Hold pin, Write Protect pin and programmable write protect, with top or bottom array control features, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification.

FEATURES

• Family of Serial Flash Memories

– W25X10L: 1M-bit / 128K-byte (131,072)

– W25X20L: 2M-bit / 256K-byte (262,144)

– W25X40L: 4M-bit / 512K-byte (524,288)

– W25X80L: 8M-bit / 1M-byte (1,048,576)

– 256-bytes per programmable page

– Uniform 4K-byte Sectors / 64K-byte Blocks

• SPI with Single or Dual Outputs

– Clock, Chip Select, Data I/O, Data Out

– Optional Hold function for SPI flexibility

• Data Transfer up to 80M-bits / second

– Clock operation to 40MHz

– Fast Read Dual Output instruction

– Auto-increment Read capability

• Flexible Architecture with 4KB sectors

– Sector Erase (4K-byte)

– Block Erase (64K-byte)

– Page program up to 256 bytes <2ms

– Minimum 100,000 erase/write cycles

– 20-year retention

• Low Power Consumption, Wide Temperature Range

– Single 2.3 to 3.3V supply

– 5mA active current, 1µA Power-down (typ)

– 0° to +85°C operating range

• Software and Hardware Write Protection

– Write-Protect all or portion of memory

– Enable/Disable protection with /WP pin

– Top or bottom array protection

• Space Efficient Packaging

– 8-pin SOIC 150-mil (W25X10L/20L/40L)

– 8-pin SOIC 208-mil (W25X40L/80L)

– 8-pin WSON 6x5-mm (W25X10L/20L/40L/80L)