W25S243A中文资料华邦电子数据手册PDF规格书

GENERAL DESCRIPTION

The W25S243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM organized as 65,536 ´ 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentiumä burst mode and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode can reduces power dissipation.

This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.

FEATURES

• Synchronous operation

• High-speed access time: 12 nS

• Single +3.3V power supply

• Individual byte write capability

• 3.3V LVTTL compatible I/O

• Clock-controlled and registered input

• Asynchronous output enable

• Pipelined/non-pipelined data output capability

• Supports snooze mode (low-power state)

• Internal burst counter supports Intel burst (Interleaved) mode & linear burst mode

• Supports 2T/1T mode

• Packaged in 128-pin QFP and TQFP