W162中文资料赛普拉斯数据手册PDF规格书

Overview

The W162 products are nine-output zero delay buffers. A Phase-Locked Loop (PLL) is used to take a time-varying signal and provide eight copies of that same signal out.

Internal feedback is used to maximize the number of output signals provided in the 16-pin package.

特性 Features

• Spread Aware™—designed to work with SSFTG reference signals

• Two banks of four outputs, plus the fed back output

• Outputs may be three-stated

• Available in 16-pin SOIC or SSOP package

• Extra strength output drive available (-19 version)

• Internal feedback