W152中文资料赛普拉斯数据手册PDF规格书

Overview

The W152 products are eight-output zero delay buffers. A Phase-Locked Loop (PLL) is used to take a time-varying signa and provide eight copies of that same signal out. The externa feedback to the PLL provides outputs in phase with the reference inputs.

Internal dividers exist in some options allowing the user to get a simple multiple (/2, x2, x4) of the reference input, for details see Table 1. Because the outputs are separated into two banks, it is possible to provide some combination of these multiples at the same time.

特性 Features

• Spread Aware™—designed to work with SSFTG reference signals

• Two banks of four outputs each

• Configuration options to halve, double, or quadruple the reference frequency refer to Table 1 to determine the specific option which meets your multiplication needs

• Outputs may be three-stated

• Available in 16-pin SOIC package

• Extra strength output drive available (-11/-12 versions)

• Contact factory for availability information on 16-pin TSSOP