V62SLASH22611-03XF中文资料德州仪器数据手册PDF规格书

1 Features

• Radiation Tolerance:

– Total Ionizing Dose (TID): 300 krad (Si)

– Single Event Latchup (SEL): 120 MeV-cm2/mg

– Single Event Upset (SEU) immune registers

• ADC core:

– 12-bit resolution

– Up to 10.4 GSPS in single-channel mode

– Up to 5.2 GSPS in dual-channel mode

• Performance specifications:

– Noise floor (–20 dBFS, VFS = 1 VPP-DIFF):

• Dual-channel mode: –151.8 dBFS/Hz

• Single-channel mode: –154.4 dBFS/Hz

– ENOB (dual channel, FIN = 2.4 GHz): 8.6 Bits

• Buffered analog inputs with VCMI of 0 V:

– Analog input bandwidth (–3 dB): 8 GHz

– Usable input frequency range: > 10 GHz

– Full-scale input voltage (VFS, default): 0.8 VPP

• Noiseless aperture delay (tAD) adjustment:

– Precise sampling control: 19-fs Step

– Simplifies synchronization and interleaving

– Temperature and voltage invariant delays

• Easy-to-use synchronization features:

– Automatic SYSREF timing calibration

– Time stamp for sample marking

• JESD204C serial data interface:

– Maximum lane rate: 17.16 Gbps

– Support for 64b/66b and 8b/10b encoding

– 8b/10b modes are JESD204B compatible

• Optional digital down-converters (DDC):

– 4x, 8x, 16x and 32x complex decimation

– Four independent 32-Bit NCOs per DDC

• Peak RF Input Power (Diff): +26.5 dBm (+ 27.5

dBFS, 560x fullscale power)

• Programmable FIR filter for equalization

• Power consumption: 4 W

• Power supplies: 1.1 V, 1.9 V

2 Applications

• Wideband digitizers

• Electronic warfare (SIGINT, ELINT)

• Satellite communications (SATCOM)

• RF-sampling software-defined radio (SDR)

3 Description

The ADC12DJ5200-SP device is an RF-sampling,

giga-sample, analog-to-digital converter (ADC) that

can directly sample input frequencies from DC to

above 10 GHz. ADC12DJ5200-SP can be configured

as a dual-channel, 5.2 GSPS ADC or single-channel,

10.4 GSPS ADC. Support of a useable input

frequency range of up to 10 GHz enables direct RF

sampling of L-band, S-band, C-band, and X-band for

frequency agile systems.

The ADC12DJ5200-SP uses a high-speed JESD204C

output interface with up to 16 serialized lanes

supporting up to 17.16 Gbps line rate. Deterministic

latency and multi-device synchronization is supported

through JESD204C subclass-1. The JESD204C

interface can be configured to trade-off line rate and

number of lanes. Both 8b/10b and 64b/66b data

encoding schemes are supported. 64b/66b encoding

supports forward error correction (FEC) for improved

bit error rates. The interface is backwards compatible

with JESD204B receivers.

Innovative synchronization features, including

noiseless aperture delay adjustment and SYSREF

windowing, simplify system design for multichannel

applications. Optional digital down converters (DDCs)

are available to provide digital conversion to

base-band and to reduce the interface rate. A

programmable FIR filter allows on-chip equalization.