V62SLASH13606-01XE中文资料德州仪器数据手册PDF规格书

1FEATURES

2• 4096 × 18-Bit Organization Array

• 7.5-ns Read and Write Cycle Time

• 3.3-V VCC, 5-V Input Tolerant

• First-Word or Standard Fall-Through Timing

• Single or Double Register-Buffered Empty and

Full Flags

• Easily Expandable in Depth and Width

• Asynchronous or Coincident Read and Write

Clocks

• Asynchronous or Synchronous Programmable

Almost-Empty and Almost-Full Flags With

Default Settings

• Half-Full Flag Capability

• Output Enable Puts Output Data Bus in High-

Impedance State

• High-Performance Submicron CMOS

Technology

• DSP and Microprocessor Interface Control

Logic

• Provide a DSP Glueless Interface to Texas

Instruments TMS320™ DSPs

• Packaged in 64-Pin Thin Quad Flat Package

SUPPORTS DEFENSE, AEROSPACE,

AND MEDICAL APPLICATIONS

• Controlled Baseline

• One Assembly and Test Site

• One Fabrication Site

• Available in Military (–55°C to 125°C)

Temperature Range

• Extended Product Life Cycle

• Extended Product-Change Notification

• Product Traceability

DESCRIPTION/ORDERING INFORMATION

The SN74V245 is a very high-speed, low-power CMOS clocked first-in first-out (FIFO) memory. It supports clock

frequencies up to 133 MHz and has read-access times as fast as 5 ns. This DSP-Sync FIFO memory features

read and write controls for use in applications such as DSP-to-processor communication, DSP-to-analog front

end (AFE) buffering, network, video, and data communications.

The SN74V245 is a synchronous FIFO, which means each port employs a synchronous interface. All data

transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable

signals. The continuous clocks for each port are independent of one another and can be asynchronous or

coincident. The enables for each port are arranged to provide a simple interface between DSPs,

microprocessors, and/or buses controlled by a synchronous interface. An output-enable (OE) input controls the

3-state output.

The synchronous FIFO has two fixed flags, empty flag/output ready (EF/OR) and full flag/input ready (FF/IR), and

two programmable flags, almost-empty (PAE) and almost-full (PAF). The offset loading of the programmable

flags is controlled by a simple state machine, and is initiated by asserting the load pin (LD). A half-full flag (HF) is

available when the FIFO is used in a single-device configuration.

Two timing modes of operation are possible with the SN74V245: first-word fall-through (FWFT) mode and

standard mode.

In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three

transitions of the RCLK signal. A read enable (REN) does not have to be asserted for accessing the first word.

In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a

specific read operation is performed. A read operation, which consists of activating REN and enabling a rising

RCLK edge, shifts the word from internal memory to the data output lines.