V62SLASH03655-01XE中文资料德州仪器数据手册PDF规格书

Controlled Baseline

– One Assembly/Test Site, One Fabrication

Site

Extended Temperature Performance of

–55°C to 125°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Enhanced Product-Change Notification

Qualification Pedigree†

EPIC (Enhanced-Performance Implanted

CMOS) Process

Inputs Are TTL-Voltage Compatible

Designed Specifically for High-Speed

Memory Decoders and Data-Transmission

Systems

Incorporates Three Enable Inputs to

Simplify Cascading and/or Data Reception

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-833, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

description/ordering information

The SN74AHCT138 3-line to 8-line decoder/demultiplexer is designed to be used in high-performance

memory-decoding and data-routing applications that require very short propagation-delay times. In

high-performance memory systems, this decoder can be used to minimize the effects of system decoding.

When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and

the enable time of the memory usually are less than the typical access time of the memory. This means that

the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two

active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.

A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one

inverter. An enable input can be used as a data input for demultiplexing applications.