V62/06662-01XE中文资料德州仪器数据手册PDF规格书

Controlled Baseline

− One Assembly Site

− One Test Site

− One Fabrication Site

Extended Temperature Performance of

−55°C to 125°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Enhanced Product-Change Notification

Qualification Pedigree†

Can Be Used as Two 16 Bit Counters or a

Single 32 Bit Counter

2-V to 5.5-V VCC Operation

Max tpd of 25 ns at 5 V (RCLK to Y)

Typical VOLP (Output Ground Bounce)

<0.7 V at VCC = 5 V, TA = 25°C

Typical VOHV (Output VOH Undershoot)

>4.4 V at VCC = 5 V, TA = 25°C

Ioff Supports Partial-Power-Down Mode

Operation

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

The SN74LV8154 is a dual 16 bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC

operation.

This 16 bit counter (A or B) feeds a 16 bit storage register and each storage register is further divided into an

upper byte and lower byte. The GAL, GAU, GBL, and GBU inputs are used to select the byte that needs to be

output at Y0−Y7. CLKA is the clock for A counter and CLKB is the clock for B counter. RCLK is the clock for the

A and B storage registers. All three clock signals are positive-edge triggered.

A 32 bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA to CLKBEN.

To ensure the high-impedance state during power up or power down, GAL, GAU, GBL, and GBU should be tied

to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability

of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.