V61C5181024中文资料茂矽电子数据手册PDF规格书

描述 Description

The V61C5181024 is a 1,048,576-bit static random-access memory organized as 131,072 words by 8 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The V61C5181024 is available in 32-pin SOJ, PDIP and TSOP.

特性 Features

■ High-speed: 10, 12, 15 ns

■ Fully static operation

■ All inputs and outputs directly TTL compatible

■ Three state outputs

■ Low data retention current (VCC = 2V)

■ Single 5V ± 10 Power Supply

■ Low CMOS Standby current of 5 mA max

■ Packages

– 32-pin TSOP

– 32-pin 300 mil SOJ