UPSD3212C-40T1T中文资料意法半导体数据手册PDF规格书

FEATURES SUMMARY

■ The uPSD321X Devices combine a Flash PSD architecture with an 8032 microcontroller core. The uPSD321X Devices of Flash PSDs feature d)ual banks of Flash memory, SRAM, general purpose I/O and programmable logic, supervisory functions and access via I2C, ADC and PWM channels, and an on-board 8032 microcontroller core, with two UARTs, three 16-bit Timer/Counters and two External Interrupts. As with other Flash PSD families, the uPSD321X Devices are also in-system programmable (ISP) via a JTAG ISP interface.

■ Large 2KByte SRAM with battery back-up option

■ Dual bank Flash memories

– 64KByte main Flash memory

– 16KByte secondary Flash memory

■ Content Security

– Block access to Flash memory

■ Programmable Decode PLD for flexible address mapping of all memories within 8032 space.

■ High-speed clock standard 8032 core (12-cycle)

■ I2C interface for peripheral connections

■ 5 Pulse Width Modulator (PWM) channels

■ Analog-to-Digital Converter (ADC)

■ Six I/O ports with up to 46 I/O pins

■ 3000 gate PLD with 16 macrocells

■ Supervisor functions with Watchdog Timer

■ In-System Programming (ISP) via JTAG

■ Zero-Power Technology

■ Single Supply Voltage

– 4.5 to 5.5V

– 3.0 to 3.6V