UPD77210中文资料瑞萨数据手册PDF规格书

FEATURES

• Instruction cycle (operating clock):

UPD77210 6.25 ns MIN. (160 MHz MAX.)

UPD77213 8.33 ns MIN. (120 MHz MAX.)

• Memory

-Internal instruction memory:

UPD77210 :RAM 31.5 Kwords x 32 bits

UPD77213 :RAM 15.5 Kwords x 32 bits

ROM 64 Kwords x 32 bits

-Data memory:

UPD77210 :RAM 30 Kwords x 16 bits x 2 planes (X and Y data memories)

External memory space 1 Mwords x 16 bits (common to X and Y data memories)

UPD77213 :RAM 18 Kwords x 16 bits x 2 planes (X and Y data memories)

ROM 32 Kwords x 16 bits x 2 planes (X and Y data memories)

External memory space 1 Mwords x 16 bits (common to X and Y data memories)

• Peripheral

-Audio serial interface: 1 channel

-Time-division serial interface: 1 channel

-16-bit host interface: 1 channel

-16-bit general-purpose port

-16-bit timer: 2 channels

-Peripheral-memory DMA transfer function

-SD (Secure Digital) card interface

:UPD77213 only