UPD77019-013中文资料瑞萨数据手册PDF规格书

16 bits, Fixed-point Digital Signal Processor

The µPD77019-013 is a masked 16 bits fixed-point DSP (Digital Signal Processor) developed for digital signal processing with its demand for high speed and precision.

The µPD77019-013 internal ROM area is masked already by the void code to use as RAM based DSP without mask code ordering process. Also the µPD77019-013 can operate as simplified evaluate chip for as the µPD7701x family.

About mask ROM and mask option, there are following differences between the µPD77019-013 and µPD77019.

FEATURES

• FUNCTIONS

• Instruction cycle: 16.6 ns (MIN.)

Operation clock: 60 MHz

External clock: 15 MHz

• Dual load/store

• Hardware loop function

• Conditional execution

• Executes product-sum operation in one instruction cycle

• PROGRAMMING

• 16 bits ×16 bits + 40 bits →40 bits multiply accumulator

• 8 general registers (40 bits each)

• 8 ROM/RAM data pointer: each data memory area has 4 registers

• 10 source interrupts (external: 4, internal: 6)

• 3 operand instructions (example: R0 = R0 +R1L∗R2L)

• Nonpipeline on execution stage

• MEMORY AREAS

• Instruction memory area : 64K words ×32 bits

• Data memory areas : 64K words ×16 bits × 2 (X memory, Y memory)

• CLOCK GENERATOR

• On-chip PLL to provide higher operation clock (60 MHz max.) than the external clock. PLL clock multiple rate is fixed to 4.

• ON-CHIP PERIPHERAL

• I/O port: 4 bits

• Serial I/O (16 bits): 2 channels

• Host I/O (8 bits): 1 channel

• CMOS

• +3 V single power supply