UPD72874中文资料IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER数据手册Renesas规格书

描述 Description

IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLERThe µPD72874 is the LSI that integrated OHCI-Link and PHY function into a single chip. The µPD72874 complies with the 1394 OHCI Specification 1.1 and the IEEE Std 1394a-2000 specifications, and works up to 400 Mbps. It makes design so compact for PC and PC card application.FEATURES
• Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.1
• Compliant with Physical Layer Services as defined in IEEE Std 1394a-2000
• Provides three cable ports at 100/200/400 Mbps
• Super Low power consumption for Physical Layer
• Compliant with protocol enhancement as defined in IEEE Std1394a-2000
• Modular 32-bit host interface compliant to PCI Specification release 2.2
• Supports PCI-Bus Power Management Interface Specification release 1.1
• Modular 32-bit host interface compliant to Card Bus Specification
• Cycle Master and Isochronous Resource Manager capable
• Built-in FIFOs for isochronous transmit (2048 bytes), asynchronous transmit (2048 bytes), and receive (3072
bytes)
• Supports D0, D1, D2, D3hot
• Supports wake up function from D3cold
• 32-bit CRC generation and checking for receive/transmit packets
• 4 isochronous transmit DMAs and 4 isochronous receive DMAs supported
• 32-bit DMA channels for physical memory read/write
• Clock generation by 24.576 MHz X’tal
• 2-wire Serial EEPROMTM interface supported
• Separate power supply Link and PHY
• Programmable latency timer from serial EEPROM in Cardbus mode (CARD_ON = 1)

特性 Features

• Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.1
• Compliant with Physical Layer Services as defined in IEEE Std 1394a-2000
• Provides three cable ports at 100/200/400 Mbps
• Super Low power consumption for Physical Layer
• Compliant with protocol enhancement as defined in IEEE Std1394a-2000
• Modular 32-bit host interface compliant to PCI Specification release 2.2
• Supports PCI-Bus Power Management Interface Specification release 1.1
• Modular 32-bit host interface compliant to Card Bus Specification
• Cycle Master and Isochronous Resource Manager capable
• Built-in FIFOs for isochronous transmit (2048 bytes), asynchronous transmit (2048 bytes), and receive (3072
bytes)
• Supports D0, D1, D2, D3hot
• Supports wake up function from D3cold
• 32-bit CRC generation and checking for receive/transmit packets
• 4 isochronous transmit DMAs and 4 isochronous receive DMAs supported
• 32-bit DMA channels for physical memory read/write
• Clock generation by 24.576 MHz X’tal
• 2-wire Serial EEPROMTM interface supported
• Separate power supply Link and PHY
• Programmable latency timer from serial EEPROM in Cardbus mode (CARD_ON = 1)