UPD72872GC-9EV中文资料瑞萨数据手册PDF规格书

FEATURES

• Shrink from the μPD72870A.

• Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0

• Compliant with Physical Layer Services as defined in P1394a draft 2.0 (Data Rate 100/200/400 Mbps)

• Numbers of supported port (1, 2 ports) are selectable

• Compliant with protocol enhancement as defined in P1394a draft 2.0

• Modular 32-bit host interface compliant to PCI local bus specification Revision 2.2

• Support PCI-Bus Power Management Interface Specification release 1.1

• Modular 32-bit host interface compliant to Card Bus Specification

• Cycle Master and Isochronous Resource Manager capable

• 32-bit CRC generation and checking for receive/transmit packets

• 4 isochronous transmit DMAs and 4 isochronous receive DMAs supported

• 32-bit DMA channels for physical memory read/write

• Clock generation by 24.576 MHz X’tal

• Internal control and operational registers direct-mapped to PCI configuration space

• 2-wire Serial EEPROMTM interface supported

• Separate power supply Link and PHY