UPD72851GT-E2中文资料瑞萨数据手册PDF规格书

FEATURES

• The one-port physical layer LSI complies with IEEE1394a-2000

• Fully interoperable with IEEE1394 std 1394 Link (FireWireTM, i.LINKTM)

• Meets IntelTM Mobile Power Guideline 2000

• Full IEEE1394a-2000 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset, multispeed

concatenation, arbitration acceleration, fly-by concatenation

• Fully compliant with OHCI requirements

• Small package: 48-pin plastic SSOP

• Super low power: 52 mA (Operating mode)

: 115 μA (Suspend mode)

• Data rate: 400/200/100 Mbps

• Supports PHY pinging and remote PHY access packets

• 3.3 V single power supply (if power not supplied via node: 3.0 V single power supply)

• 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency

• 64-bit flexible register incorporated in PHY register

• Electrically isolated Link interface

• Supports LPS/Link-on as part of PHY/Link interface

• External filter capacitors for PLL not required

• Extended Resume signaling for compatibility with legacy DV devices

• System power management by signaling of node power class information

• Cable power monitor (CPS) is equipped