UPD72850A中文资料瑞萨数据手册PDF规格书

FEATURES

• The Three-port Physical Layer LSI complies to IEEE P1394a draft 2.0

• Connection debounce

• Arbitration enhancements

• Arbitrated short bus reset

• Ack-accelerated arbitration

• Fly-by concatenation

• Multiple-speed packet concatenation

• Arbitration enhancements and cycle start (controlled by the Link layer)

• Performance optimization via PHY pinging

• Priority arbitration (controlled by the Link layer)

• Data rate: 393.216 / 196.608 / 98.304 Mbps

• Compliant with Suspend/Resume function as defined in P1394a draft 2.1

• 3.3 V single power supply

• Electrical isolated Link interface

• 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency

• System power management by signaling of node power class information

• Cable power monitor (CPS) is equipped

• Fully interoperable with IEEE1394 std 1394 Link (FireWireTM, i.LINKTM)

• Cable bias and terminal voltage driver supply function (for 3-port each)

• Separate digital power and analog GND

• Enable/Disable port control switch when power supply is powered on