UPD70732R-25中文资料瑞萨数据手册PDF规格书

特性 Features

High-performance 32-bit architecture for embedded control application

• 32-bit separate address/data bus

• 1-Kbyte cache memory

• Pipeline structure of 1 clock pitch

• 16-bit fixed instructions (with some exceptions)

• 32-bit general-purpose registers: 32

• 4-Gbyte linear address space

• Register/flag hazard interlocked by hardware

Dynamic bus sizing function (16 bits)

16-bit bus fixing function

16-bit bus system can be configured.

Instructions ideal for various application fields

• Floating-point operation instructions (based upon IEEE754 data format)

• Bit string instructions

16 levels of high-speed interrupt responses

Clock can be stopped by internal static operation

Maximum operating frequency: 16/20/25 MHz

Low voltage: VDD = 2.7 to 3.6 V (Max. 16 MHz)

VDD = 2.2 to 3.6 V (Max. 10 MHz)

Small package versions available (14 x 14 mm fine-pitch TQFP)