UPD705100中文资料瑞萨数据手册PDF规格书

FEATURES

• High-performance 32-bit architecture for

incorporation use

• Built-in cache memory

Instruction cache : 4K bytes

Data cache : 4K bytes

• Built-in RAM

Instruction RAM : 4K bytes

Data RAM : 4K bytes

• One-clock-pitch pipeline structure

• 16-/32-bit instructions

• Separate buses for addresses and data

• 4G-byte linear addresses

• Thirty-two 32-bit general-purpose registers

• Hardware-interlocked register/flag hazard

• 16-level interrupt responses