UPD45128163-I-E中文资料美光科技数据手册PDF规格书

描述 Description

The µPD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as 2,097,152 ×16 ×4 (word ×bit ×bank). The synchronous DRAM achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAM is compatible with Low Voltage TTL (LVTTL).

This product is packaged in 54-pin TSOP (II).

特性 Features

•Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge

•Pulsed interface

•Possible to assert random column address in every cycle

•Quad internal banks controlled by BA0(A13) and BA1(A12)

•Byte control by LDQM and UDQM

•Programmable Wrap sequence (Sequential / Interleave)

•Programmable burst length (1, 2, 4, 8 and full page)

•Programmable /CAS latency (2 and 3)

•Ambient temperature (TA): −40 to + 85°C

•Automatic precharge and controlled precharge

•CBR (Auto) refresh and self refresh

• ×16 organization

•Single 3.3 V ±0.3 V power supply

•LVTTL compatible inputs and outputs

•4,096 refresh cycles / 64 ms

•Burst termination by Burst stop command and Precharge command

•TSOP (II) package with lead free solder (Sn-Bi)

RoHS compliant